1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device including a semiconductor layer formed on an insulating film and a manufacturing method thereof.
2. Description of the Background Art
In order to contemplate a high performance semiconductor, an attempt has been done to manufacture a semiconductor integrated circuit having small stray capacitance by separating circuit elements by dielectric substance. When a transistor is formed in a thin silicon layer formed on an insulating film (referred to as "SOI (Silicon On Insulator) layer" hereinafter), so-called MESA isolation method is employed in order to separate the element circuits.
It has been reported that each transistor isolated by this method has many advantages since it is formed as a completely island-like semiconductor layer. For example, the transistor is not affected by latch up with an adjacent transistor.
FIGS. 39-41 show plan and cross sectional views of an MOS field-effect transistor (referred to as "MOS FET" hereinafter) which is formed in an SOI layer formed by the conventional MESA isolation method. FIG. 39 shows a plan view of the SOI layer MOS FET. Referring to FIG. 39, an SOI layer 103 is formed like an island on a buried oxide film 102. A gate electrode 105 is formed such that it traverses SOI layer 103. A contact hole 190 is formed such that it connects the source and drain of the transistor. A wiring layer 193 is formed such that it electrically contacts the source/drain regions within contact hole 190.
FIG. 40 is a cross sectional view taken along line 600--600 of FIG. 39. Referring to FIG. 40, buried oxide film 102 is formed on a silicon substrate 101. SOI layer 103 is formed at a predetermined region on a main surface of buried oxide film 102. On both a main surface of SOI layer 103 and a predetermined region on the main surface of buried oxide film 102, gate electrode layer 105 is formed. A gate insulating film 106 is formed between SOI layer 103 and gate electrode layer 105. An interlayer insulating film 109 is formed such that it covers gate electrode layer 105.
FIG. 41 is a cross sectional view taken along line 500--500 of FIG. 39. Referring to FIG. 41, buried oxide film 102 is formed such that it contacts substrate 101. SOI layer 103 is formed on buried oxide film 102. A sidewall insulating film 116 is formed at both side ends of SOI layer 103. A silicide layer 108 is formed at a predetermined region on the main surface of SOI layer 103. Formed on gate insulating film 106 are gate electrode 105, and sidewall insulating film 116 positioned at both side ends of gate electrode 105. Silicide layer 108 is formed on a surface of gate electrode 105. Interlayer insulating film 109 is formed such that it covers the transistor. A metal wiring 110 is formed such that it contacts silicide layer 108 formed on the source/drain regions of SOI layer 103.
FIGS. 42-71 illustrate a manufacturing process of the semiconductor shown in FIGS. 39-41. Referring to FIGS. 42-71, a conventional semiconductor manufacturing process will be described. FIG. 42 shows an example in which buried oxide film 102 is formed on silicon substrate 101 and SOI layer 103 is further formed thereon. Silicon substrate 101, buried oxide film 102 and SOI layer 103 constitute an SOI substrate. By oxidizing a surface of SOI layer 103, an oxide film 104 is formed which has a thickness of 100-200 .ANG..
As shown in FIG. 43, a nitride film 125 is formed on a main surface of oxide layer 104. As shown in FIG. 44, a resist 100 is formed on a predetermined region on a main surface of nitride film 125. As shown in FIG. 45, nitride film 125, oxide film 104 and SOI layer 103 are etched by using resist 100 as a mask. Then, as shown in FIG. 46, resist 100 is removed.
FIG. 47 is a cross-sectional view of the stage shown in FIG. 46, taken along line 600--600. SOI layer 103, oxide film 104 and nitride film 125 are formed on a predetermined region on a main surface of buried oxide film 102.
Then, as shown in FIGS. 48 and 49, SOI layer 103 is oxidized. FIGS. 48 and 49 illustrate the initial stage of the oxidizing process; FIG. 48 showing a cross-sectional view taken along line 500--500 of FIG. 39, and FIG. 49 is a cross-sectional view taken along line 600--600 of FIG. 39. Referring to FIG. 49, oxidizing agent 146 is diffused and reaches SOI layer 103 to oxidize SOI layer 103.
FIGS. 50 and 51 are cross sectional views in which the oxidizing process is completed. FIGS. 50 and 51 are cross sectional views taken along lines 500--500 and 600--600, respectively. Referring to FIG. 51, as the oxidizing process proceeds, lower part of SOI layer 103 is oxidized. The lower part of SOI layer 103 is thereby lifted upward, and SOI layer 103 is curved upward. Furthermore, an upper side end 103b of SOI layer 103 is rounded by the oxidation.
FIGS. 52 and 53 show a state in which nitride film 125 is removed after the oxidizing process is completed. FIGS. 52 and 53 are cross sectional views taken along lines 500--500 and 600--600, respectively.
As shown in FIG. 54, resist 100 is formed on a P-type MOS region. By using resist 100 as a mask, boron ions are implanted into an N-type MOS region. This ion-implantation serves as a channel-implantation of N-type MOSFET.
After resist 100 formed on the P-type MOS region is removed, resist 100 is again formed on the N-type MOS region, as shown in FIG. 55. By using resist 100 as a mask, phosphorus ions are implanted into the P-type M0S region. This ion-implantation serves as a channel-implantation of P-type MOSFET. Resist 100 is then removed.
Then, by removing oxide film 104, a shape as shown in FIG. 56 is obtained. FIG. 57 is a cross sectional view, taken along line 600--600, after oxide film 104 is removed. Referring to FIG. 57, buried oxide film 102 which had existed under a curved portion 103f of SOI layer 103 was removed when oxide film 104 was removed.
As shown in FIGS. 58 and 59, an oxide film 106 is then formed on a surface of SOI layer 103. Oxide film 106 serves as a gate oxide film of the transistor.
As shown in FIG. 60, a polysilicon layer 105 is formed on the entire surface to a thickness of approximately 2000 .ANG.. FIG. 61 is a cross sectional view, taken along line 600--600, of the stage shown in FIG. 60. The polysilicon layer 105 is formed such that it intrudes under the curved portion of SOI layer 103.
Resist 100 is then formed at a predetermined region on polysilicon layer 105, as shown in FIG. 62. Resist 100 is used as a mask and, as shown in FIG. 63, polysilicon layer 105 is selectively removed by etching.
As shown in FIG. 64, resist 100 is formed only on the N-type MOS region and boron ions are implanted into the P-type MOS region. This implantation serves as an LDD implantation of P-type MOSFET. As shown in FIG. 65, resist 100 is formed only on the P-type MOS region and phosphorus ions are implanted into the N-type MOS region. This implantation serves as an LDD implantation of N-type MOSFET.
After resist 100 is removed, an insulating film 116a is formed on the entire surface, as shown in FIG. 66.
By anisotropically etching insulating film 116a, a sidewall insulating film 116 is formed as shown in FIG. 67.
As shown in FIG. 68, resist 100 is formed only on the N-type MOS region and boron ions are implanted into the P-type MOS region. This implantation serves as a source/drain implantation of the P-type MOSFET. Resist 100 is then removed.
As shown in FIG. 69, resist 100 is again formed only on the P-type MOS region and arsenic ions are implanted into the N-type M0S region. This implantation serves as a source/drain implantation of the N-type MOSFET. Resist 100 is then removed.
A silicide layer 108 is formed on a surface of SOI layer 103 and on a surface of gate electrode 105, as shown in FIG. 70. An interlayer insulating film 109 is then formed to a thickness of approximately 7000 .ANG.. Then, after a contact hole (not shown) is formed for connecting to the source/drain regions, a metal wiring 110 is formed by forming a metal layer mainly consisting of aluminum using the sputtering method. FIG. 71 is a cross sectional view, taken along line 600--600, of the stage shown in FIG. 70. As can be seen, SOI layer 103 is curved upward at its both ends. Furthermore, gate electrode 106 is formed such that it intrudes under the curved portion of SOI layer 103.
Thus, the conventional semiconductor device shown in FIGS. 39-41 is accomplished.
As described above, according to the conventional semiconductor manufacturing method, an end portion of SOI layer 103 is curved upward by the process of oxidizing SOI layer 103. This process of oxidizing a side wall of SOI layer 103 contemplates oxidizing and absorbing a region damaged by etching that remains in SOI layer 103 side wall when SOI layer 103 is dry-etched. For this reason, the oxidizing process is important. In other words, if the side wall is not oxidized, the region damaged by etching causes increased leakage current, and uniformity of the transistor deteriorates. Furthermore, as oxidation proceeds, lower part of SOI layer 103 is oxidized and SOI layer 103 is thereby lifted upward. Thus, SOI layer 103 is curved upward. The curved SOI layer 103 causes problems described below.
Firstly, as SOI layer 103 is curved, internal stress occurs resulting in crystal defect in SOI layer 103. The crystal defect increases leakage current of the transistor when the transistor is formed thereafter. This is problematic because it deteriorates electrical performance of the transistor.
Secondly, as SOI layer 103 is curved upward, a gate electrode intrudes under a lower part of SOI layer 103 when the gate electrode is formed in the process thereafter. For this reason, threshold voltage of this region is lowered and as a result, a hump is formed in subthreshold characteristic. This adversely affects electrical characteristic of the transistor formed.